Not applicable.
Not applicable.
1. Field of the Invention
This invention relates generally to computer system microprocessors. More particularly, the invention relates to the use of clock skipping techniques to transfer data between different clock domains.
2. Background of the Invention
In simple computer systems, a single clock signal may be used to run all of the devices which are integrated into the microprocessor chip. As shown in FIG. 1, a system clock 11 may provide a clock signal to a microprocessor or central processing unit (xe2x80x9cCPUxe2x80x9d) 12, a memory 13 and a peripheral device 14 via clock line 16. The signal on clock line 16 is used to clock data transfers between the devices on bus 15.
While implementation of the system illustrated in FIG. 1 is simple and relatively straightforward, its simplicity results in performance limitations. One of these limitations relates to variations in the clock signal seen by devices on the chip. The use of a network of conductive traces to deliver the clock signal to each of the devices causes reflections, noise and other uncertainties in the signal. These factors cause differences in the signals delivered to different devices, which may in turn limit the devices"" ability to communicate data.
In the simple system illustrated in FIG. 1, a data transfer involves two devices in the same clock domain. The term xe2x80x9cclock domainxe2x80x9d refers to a portion of a system in which the operation of associated devices is based on a particular clock signal. Thus, the operations of the devices in that particular clock domain are based upon clock signals having the same frequency. In the absence of any clock skew, data transferred from one of these devices to the other must be asserted for a period of time before the data is sampled (the setup time) and a period of time after the data is sampled (the hold time.) If there is any skew, differences in clock signals caused by propagation times to various components, reflections, etc., between the clock signals at each of the devices, the assertion of the data must be maintained for an additional amount of time which is long enough to account for this difference. While this additional time may not be significant in relation to slower clock speeds, high-speed microprocessors have shorter clock periods so it may not be possible to perform data transfers quickly enough to keep up with the speed of the processor.
Clock forwarding is one technique used to minimize the impact of clock skew and allow improved performance in data transfers. In a clock forwarding scheme, the data bus and system clock described above are replaced by point-to-point data and clock signals. When data transfers from one device to another, it transfers along with a corresponding clock signal. Referring to FIG. 2, data transfers on one or more data lines 18 while a clock signal forwards on clock line 19. Data clocks into a series of storage locations (i.e. flip-flops) according to the forwarded clock signal. Data clocks out of the storage locations according to a clock signal of the receiving device (not shown). Both clock signals must have the same rate, but a substantial skew in the signals will not prevent reliable transfer of the data.
While clock forwarding techniques transfer data between devices operating at the same clock rate, it is often desirable in modern computer systems to use different clock frequencies for different devices. For example, it may be useful to operate the core logic (i.e., the microprocessor logic) and the system or peripheral logic at different frequencies. The difference in frequencies allows for advances in the performance of one type of logic without requiring equal advances in the other type of logic. Thus, for example, the processor speed can be increased without having to also speed up the system logic.
In these systems, system logic (logic on the microprocessor chip that interfaces the high speed core logic to the remaining, lower speed, system components) is closely tied to the system bus (the bus across which the microprocessor communicates with the rest of the computer system). System logic of the prior art operates at a frequency which is an integer or half-integer multiple of the system bus frequency. Because the system logic operates at a frequency which is a multiple of the system bus frequency, clock signals for the system logic can be generated from the same clock as the clock signals for the system bus. If the core logic also runs at a frequency which is an integer or half-integer multiple of the system bus frequency, it can also be easily generated from the system bus clock signal. For example, if the system bus is running at 66 MHz, the system logic and core logic can be operated at 200 MHz (three times the system bus frequency). Then, if desired, the frequency of the core logic can be scaled up to 266 MHz (four times the system bus frequency), while the system logic remains at 200 MHz.
As the operating frequency of the system bus increases, however, it becomes more and more difficult to scale up the speed of the core logic because this requires a larger increase in frequency. For example, if the system bus is running at 400 MHz and both the core logic and the system logic are running at 800 MHz, in the prior art the core logic cannot easily scale up to 900 MHz because 900 MHz is not an integer or half-integer multiple of the system bus frequency. It may therefore be useful in operating the core logic at non-integer or non-half-integer frequencies to operate the different sets of logic using multiple clocks.
While having multiple clock sources may solve the problems associated with operating the core logic at non-integer and non-half-integer frequencies, new problems arise associated with transferring information between the two clock domains. For example, in a write operation from the higher frequency clock domain to the lower frequency domain, even in a clock forwarded arrangement, the higher frequency clock domain overruns the lower frequency clock domain unless steps are taken to prevent this. In the prior art, this problem was addressed by periodically and systematically skipping clock pulses of the higher frequency clock domain such that the lower frequency clock domain removed data from interface buffers at the same rate as the effective transfer clock domain. However, calculating which clock pulses of the higher frequency clock to skip in the prior art is cumbersome. For example, a computer system designer of the prior art may have had to calculate a skip pattern for each ratio of core frequency to system frequency for which the computer system would operate before the system implementation of the computer system.
Thus, it would be desirable to have a skip signal generation circuit that can calculate skip patterns to insure proper transfer of information between respective clock domains without having to work out those patterns in advance and without the requirement of the ratio of the core frequency to the system bus frequency being integer or half-integer.
The problems noted above are solved in large part by a system and related method for transferring data from a first clock domain to a second clock domain, wherein the ratio of the clock rates is not constrained to be an integer or half-integer multiples. This is accomplished by use of a skip signal generation circuit preferably integrated onto the microprocessor substrate. The skip signal generation circuit reads increment values related to the peripheral frequency and the core frequency. The manufacturer writes this information in the microprocessor during manufacture by means of fusible links on the microprocessor substrate. Alternatively, in a computer system adapted to lower microprocessor operating frequencies, possibly to reduce power consumption, the increment values are those values supplied by external programs and hardware, possibly the basic input/output system (xe2x80x9cBIOSxe2x80x9d). The skip signal generation circuit calculates, substantially simultaneously with the data transfer, a skip signal which signifies the need to skip a clock pulse of the faster clock during data transfer between two clock domains. The skip generation circuit makes this determination by counting in increments related to the core frequency and the system or peripheral frequency. By comparing the count values associated with each of the core and peripheral or system frequencies, the skip signal generation circuit generates skip signals as necessary for the particular ratio of system frequency to core frequency. This ratio need not be an integer or half-integer relationship.